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CMOS SyncBiFIFOTM WITH BUS MATCHING AND BYTE SWAPPING 64 x 36 x 2
Integrated Device Technology, Inc.
IDT723614
FEATURES:
* Free-running CLKA and CLKB can be asynchronous or coincident (simultaneous reading and writing of data on a single clock edge is permitted) * Two independent clocked FIFOs (64 x 36 storage capacity each) buffering data in opposite directions * Mailbox bypass Register for each FIFO * Dynamic Port B bus sizing of 36-bits (long word), 18-bits (word), and 9-bits (byte) * Selection of Big- or Little-Endian format for word and byte bus sizes * Three modes of byte-order swapping on port B * Programmable Almost-Full and Almost-Empty Flags
Microprocessor interface control logic EFA, FFA, AEA, and AFA flags synchronized by CLKA EFB, FFB, AEB, and AFB flags synchronized by CLKB Passive parity checking on each port Parity generation can be selected for each port Low-power advanced BiCMOS technology Supports clock frequencies up to 67 MHz Fast access times of 10 ns Available in 132-pin plastic quad flat package (PQF) or space-saving 120-pin thin quad flat package (TQFP) * Industrial temperature range (-40C to +85C) is available, tested to military electrical specifications
* * * * * * * * *
FUNCTIONAL BLOCK DIAGRAM
CLKA W/RA ENA MBA
CSA
Port-A Control Logic Mail 1 Register Parity Gen/Check
MBF1 PEFB
PGB
Byte Matching & Byte Swapping
Parity Generation
Input Register
RST EVEN
ODD/
64 x 36 SRAM
Output Register
36
Device Control
Write Pointer
Read Pointer
FFA AFA
FS0 FS1 A0 - A35
Status Flag Logic
36
FIFO1 Programmable Flag Offset Register FIFO2 Status Flag Logic Read Pointer Write Pointer
EFB AEB
B0-B35
EFA AEA
FFB AFB
36
Bus Matching & Byte Swapping
Parity Generation
Output Register
64 x 36 SRAM
PGA Parity Gen/Check
Mail 2 Register
PEFA MBF2
Input Register
Port-B Control Logic
CLKB
CSB BE
W/RB ENB SIZ0 SIZ1 SW0 SW1
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The IDT logo is a registered trademark and SyncBiFIFO is a trademark of Integrated Device Technology, Inc.
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(c)1997 Integrated Device Technology, Inc For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
MAY 1997
DSC-3146/4
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IDT723614 CMOS SyncBiFIFOTM WITH BUS MATCHING AND BYTE SWAPPING 64 x 36 x 2
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DESCRIPTION:
The IDT723614 is a monolithic, high-speed, low-power BiCMOS bidirectional clocked FIFO memory. It supports clock frequencies up to 67MHz and has read access times as fast as 10ns. Two independent 64 x 36 dual-port SRAM FIFOs on board the chip buffer data in opposite directions. Each FIFO has flags to indicate empty and full conditions and two programmable flags (almost-full and almost-empty) to indicate when a selected number of words is stored in memory. FIFO data on port B can be input and output in 36-bit, 18-bit, and 9-bit formats with a choice of big- or little-endian configurations. Three modes of byte-order swapping are possible
with any bus size selection. Communication between each port can bypass the FIFOs via two 36-bit mailbox registers. Each mailbox register has a flag to signal when new mail has been stored. Parity is checked passively on each port and may be ignored if not desired. Parity generation can be selected for data read from each port. Two or more devices can be used in parallel to create wider data paths. The IDT723614 is a clocked FIFO, which means each port employs a synchronous interface. All data transfers through a port are gated to the LOW-to-HIGH transition of a continuous (free-running) port clock by enable signals. The clocks for each port are independent of one another and can be asyn-
PIN CONFIGURATIONS
MBA FS1 FS0 ODD/EVEN
ENA CLKA W/RA VCC PGA
GND A0 A1 A2 GND A3 A4 A5 A6 VCC A7 A8 A9 GND A10 A11 VCC A12 A13 A14 GND A15 A16 A17 A18 A19 A20 GND A21 A22 A23
AEA EFA
VCC A24 A25 A26 GND A27 A28 A29 VCC A30 A31 A32 GND A33 A34 A35 GND B35 B34 B33 GND B32 B31 B30 VCC B29 B28 B27 GND B26 B25 B24 VCC
51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117
PGB VCC W/RB CLKB ENB
PEFA GND MBF2
MBF1
SW1 SW0 SIZ1 SIZ0
PEFB
GND
GND
AFA FFA CSA
CSB FFB AFB
116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 GND
RST
BE
*
AEB EFB
B0 B1 B2 GND B3 B4 B5 B6 VCC B7 B8 B9 GND B10 B11 VCC B12 B13 B14 GND B15 B16 B17 B18 B19 B20 GND B21 B22 B23
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*El
ectrical pin 1 in center of beveled edge. Pin 1 identifier in corner.
PQFP (PQ132-1, order code: PQF) TOP VIEW
NOTES: 1. NC - No internal connection. 2. Uses Yamaichi socket IC51-1324-828.
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IDT723614 CMOS SyncBiFIFOTM WITH BUS MATCHING AND BYTE SWAPPING 64 x 36 x 2
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chronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses controlled by a synchronous interface. The full flag (FFA, FFB) and almost-full flag (AFA, AFB) of a FIFO are two-stage synchronized to the port clock that
writes data to its array. The empty flag (EFA, EFB) and almostempty (AEA, AEB) flag of a FIFO are two stage synchronized to the port clock that reads data from its array. The IDT723614 is characterized for operation from 0C to 70C.
PIN CONFIGURATIONS (CONT.)
A24 A25 A26 VCC A27 A28 A29 GND A30 A31 A32 A33 A34 A35 GND B35 B34 B33 B32 B31 B30 GND B29 B28 B27 VCC B26 B25 B24 B23
A23 A22 A21 GND A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 GND A9 A8 A7 VCC A6 A5 A4 A3 GND A2 A1 A0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91
EFA AEA
90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
B22 B21 GND B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 GND B9 B8 B7 VCC B6 B5 B4 B3 GND B2 B1 B0
EFB AEB AFB
MBA FS1 FS0 ODD/EVEN
ENA CLKA W/RA VCC PGA
AFA FFA CSA
PEFA MBF2
MBF1 PEFB
PGB VCC W/RB CLKB ENB
SW1 SW0 SIZ1 SIZ0
GND
CSB FFB
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RST
TQFP (PN120-1, order code: PF) TOP VIEW
BE
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
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IDT723614 CMOS SyncBiFIFOTM WITH BUS MATCHING AND BYTE SWAPPING 64 x 36 x 2
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PIN DESCRIPTION
Symbol Name A0-A35 Port A Data I/O I/O Description 36-bit bidirectional data port for side A.
AEA AEB AFA AFB
B0-B35
Port A Almost-Empty Flag Port B Almost-Empty Flag Port A Almost-Full Flag Port B Almost-Full Flag Port B Data. Big-endian select
O Programmable almost-empty flag synchronized to CLKA. It is LOW when (Port A) the number of 36-bit words in FIFO2 is less than or equal to the value in the offset register, X. O Programmable almost-empty flag synchronized to CLKB. It is LOW when the (Port B) number of 36-bit words in FIFO1 is less than or equal to the value in the offset register, X. O Programmable almost-full flag synchronized to CLKA. It is LOW when the (Port A) number of 36-bit empty locations in FIFO1 is less than or equal to the value in the offset register, X. O Programmable almost-full flag synchronized to CLKB. It is LOW when the (Port B) number of 36-bit empty locations in FIFO2 is less than or equal to the value in the offset register, X. I/O I 36-bit bidirectional data port for side B. Selects the bytes on port B used during byte or word data transfer. A LOW on BE selects the most significant bytes on B0-B35 for use, and a HIGH selects the least significant bytes CLKA is a continuous clock that synchronizes all data transfers through port A and can be asynchronous or coincident to CLKB. EFA, FFA, AFA, and AEA are synchronized to the LOW-to-HIGH transition of CLKA. CLKB is a continuous clock that synchronizes all data transfers through port B and can be asynchronous or coincident to CLKA. Port B byte swapping and data port sizing operations are also synchronous to the LOW-to-HIGH transition of CLKB. EFB, FFB, AFB, and AEB are synchronized to the LOW-to-HIGH transition of CLKB. CSA must be LOW to enable a LOW-to-HIGH transition of CLKA to read or write data on port A. The A0-A35 outputs are in the high-impedance state when CSA is HIGH.
BE
CLKA
Port A Clock
I
CLKB
Port B Clock
I
CSA CSB EFA
Port A Chip Select
I
Port B Chip Select
I
Port A Empty Flag
EFB
Port B Empty Flag
ENA ENB
Port A Enable Port B Enable Port A Full Flag
write data on port B. The B0-B35 outputs are in the high-impedance state when CSB is HIGH. O EFA is synchronized to the LOW-to-HIGH transition of CLKA. When EFA is (Port A) LOW, FIFO2 is empty, and reads from its memory are disabled. Data can be read from FIFO2 to the output register when EFA is HIGH. EFA is forced LOW when the device is reset and is set HIGH by the second LOW-to-HIGH transition of CLKA after data is loaded into empty FIFO2 memory. O EFB is synchronized to the LOW-to-HIGH transition of CLKB. When EFB is (Port B) LOW, the FIFO1 is empty, and reads from its memory are disabled. Data can be read from FIFO1 to the output register when EFB is HIGH. EFB is forced LOW when the device is reset and is set HIGH by the second LOW-to-HIGH transition of CLKB after data is loaded into empty FIFO1 memory. I ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data on port A. I ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write data on port B. O FFA is synchronized to the LOW-to-HIGH transition of CLKA. When FFA is (Port A) LOW, FIFO1 is full, and writes to its memory are disabled. FFA is forced LOW when the device is reset and is set HIGH by the second LOW-to-HIGH transition of CLKA after reset. O FFB is synchronized to the LOW-to-HIGH transition of CLKB. When FFB is (Port B) LOW, FIFO2 is full, and writes to its memory are disabled. FFB is forced LOW when the device is reset and is set HIGH by the second LOW-to-HIGH transition of CLKB after reset.
CSB must be LOW to enable a LOW-to-HIGH transition of CLKB to read or
FFA FFB
Port B Full Flag
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IDT723614 CMOS SyncBiFIFOTM WITH BUS MATCHING AND BYTE SWAPPING 64 x 36 x 2
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PIN DESCRIPTION (CONTINUED)
Symbol Name I/O I Description The LOW-to-HIGH transition of RST latches the values of FS0 and FS1, which selects one of four preset values for the almost-full flag and almost-empty flag offset. A HIGH level on MBA chooses a mailbox register for a port A read or write operation. When the A0-A35 outputs are active, a HIGH level on MBA selects data from the mail2 register for output, and a LOW level selects FIFO2 output register data for output. MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the mail1 register. Writes to the mail1 register are inhibited while MBF1 is set LOW. MBF1 is set HIGH by a LOW-to-HIGH transition of CLKB when a port B read is selected and both SIZ1 and SIZ0 are HIGH. MBF1 is set HIGH when the device is reset. MBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the mail2 register. Writes to the mail2 register are inhibited while MBF2 is set LOW. MBF2 is set HIGH by a LOW-to-HIGH transition of CLKA when a port A read is selected and MBA is HIGH. MBF2 is set HIGH when the device is reset. Odd parity is checked on each port when ODD/EVEN is HIGH, and even parity is checked when ODD/EVEN is LOW. ODD/EVEN also selects the type of parity generated for each port if parity generation is enabled for a readoperation.
FS1, FS0 Flag-Offset Selects
MBA
Port A Mailbox Select
I
MBF1
Mail1 Register Flag
O
MBF2
Mail2 Register Flag
O
EVEN PEFA
ODD/
Odd/Even Parity Select Port A Parity Error Flag
I
O When any byte applied to terminals A0-A35 fails parity, PEFA is LOW. Bytes are (Port A) organized as A0-A8, A9-A17, A18-A26, and A27-A35, with the most significant bit of each byte serving as the parity bit. The type of parity checked is deter mined by the state of the ODD/EVEN input. The parity trees used to check the A0-A35 inputs are shared by the mail2 register to generate parity if parity generation is selected by PGA. Therefore, if a mail2 read parity generation is setup by having W/RA LOW, MBA HIGH, and PGA HIGH, the PEFA flag is forced HIGH regardless of the A0-A35 inputs. O When any valid byte applied to terminals B0-B35 fails parity, PEFB is LOW. Bytes (Port B) are organized as B0-B8, B9-B17, B18-B26, B27-B35 with the most significant bit of each byte serving as the parity bit. A byte is valid when it is used by the bus size selected for Port B. The type of parity checked is determined by the state of the ODD/EVEN input. The parity trees used to check the B0-B35 inputs are sharedby the mail 1 register to generate parity if parity generation isselected by PGB. Therefore, if a mail1 read with parity generation is setup by having W/RB LOW, SIZ1 and SIZ0 HIGH, and PGB HIGH, the PEFB flag is forced HIGH regardless of the state of the B0-B35 inputs. I Parity is generated for data reads from port A when PGA is HIGH. The type of parity generated is selected by the state of the ODD/EVEN input. Bytes are organized as A0-A8, A9-A17, A18-A26, and A27-A35. The generated parity bits are output in the most significant bit of each byte. I Parity is generated for data reads from port B when PGB is HIGH. The type of parity generated is selected by the state of the ODD/EVEN input. Bytes are organized as B0-B8, B9-B17, B18-B26, and B27-B35. The generated parity bits are output in the most significant bit of each byte. I To reset the device, four LOW-to-HIGH transitions of CLKA and four LOW-toHIGH transitions of CLKB must occur while RST is LOW. This sets the AFA, AFB, MBF1, and MBF2 flags HIGH and the EFA, EFB, AEA, AEB, FFA, and FFB flags LOW. The LOW-to-HIGH transition of RST latches the status of the FS1 and FS0 inputs to select almost-full and almost-empty flag offsets
PEFB
Port B Parity Error Flag
PGA
Port A Parity Generation
PGB
Port B Parity Generation
RST
Reset
SIZ0, SIZ1 Port B bus size selects
I A LOW-to-HIGH transition of CLKB latches the states of SIZ0, SIZ1, and BE, and (Port B) the following LOW-to-HIGH transition of CLKB implements the latched states as a port B bus size. Port B bus sizes can be long word, word, or byte. A high on both SIZ0 and SIZ1 accesses the mailbox reegisters for a port B 36-bit write or read.
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IDT723614 CMOS SyncBiFIFOTM WITH BUS MATCHING AND BYTE SWAPPING 64 x 36 x 2
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PIN DESCRIPTION (CONTINUED)
Symbol Name SW0, SW1 Port B byte swap Select I/O Description I At the beginning of each long word transfer, one of four modes of byte-order (Port B) swapping is selected by SW0 and SW1. The four modes are no swap, byte swap, word swap, and byte-word swap. Byte-order swapping is possible with any bus-size selection. I A HIGH selects a write operation and a LOW selects a read operation on port A for a LOW-to-HIGH transition of CLKA. The A0-A35 outputs are in the high-impedance state when W/RA is HIGH. I A HIGH selects a write operation and a LOW selects a read operation on port B for a LOW-to-HIGH transition of CLKB. The B0-B35 outputs are in the high-impedance state when W/RB is HIGH.
W/RA
Port A Write/Read Select Port B Write/Read Select
W/RB
SIGNAL DESCRIPTIONS
RESET The IDT723614 is reset by taking the reset (RST) input LOW for at least four port A clock (CLKA) and four port B clock (CLKB) LOW-to-HIGH transitions. The reset input can switch asynchronously to the clocks. A device reset initializes the internal read and write pointers of each FIFO and forces the full flags (FFA, FFB) LOW, the empty flags (EFA, EFB) LOW, the almost-empty flags (AEA, AEB) LOW and the almost-full flags (AFA, AFB) HIGH. A reset also forces the mailbox flags (MBF1, MBF2) HIGH. After a reset, FFA is set HIGH after two LOW-to-HIGH transitions of CLKA and FFB is set HIGH after two LOW-to-HIGH transitions of CLKB. The device must be reset after power up before data is written to its memory. A LOW-to-HIGH transition on the RST input loads the almost-full and almost-empty offset register (X) with the values selected by the flag-select (FS0, FS1) inputs. The values that can be loaded into the registers are shown in Table 1. FIFO WRITE/READ OPERATION The state of port A data A0-A35 outputs is controlled by the port A chip select (CSA) and the port A write/read select (W/RA). The A0-A35 outputs are in the high-impedance state when either CSA or W/RA is HIGH. The A0-A35 outputs are active when both CSA and W/RA are LOW. Data is loaded into FIFO1 from the A0-A35 inputs on a LOW-to-HIGH transition of CLKA when CSA is LOW, W/RA is HIGH, ENA is HIGH, MBA is LOW, and FFA is HIGH. Data is read from FIFO2 to the A0-A35 outputs by a LOW-to-HIGH transition of CLKA when CSA is LOW, W/RA is LOW, ENA is HIGH, MBA is LOW, and EFA is HIGH (see Table 2). The port B control signals are identical to those of port A. The state of the port B data (B0-B35) outputs is controlled by the port B chip select (CSB) and the port B write/read select (W/RB). The B0-B35 outputs are in the high-impedance state when either CSB or W/RB is HIGH. The B0-B35 outputs are active when both CSB and W/RB are LOW. Data is loaded into FIFO2 from the B0-B35 inputs on a LOW-to-HIGH transition of CLKB when CSB is LOW, W/RB is HIGH, ENB is HIGH, EFB is HIGH, and either SIZ0 or SIZ1 is LOW. Data is read from FIFO1 to the B0-B35 outputs by a LOW-to-HIGH transition of CLKB when CSB is LOW, W/RB is LOW, ENB is HIGH, EFB is HIGH, and either SIZ0 or SIZ1 is LOW (see Table 3). The setup and hold time constraints to the port clocks for the port chip selects (CSA, CSB) and write/read selects (W/ RA, W/RB) are only for enabling write and read operations and are not related to high-impedance control of the data outputs. If a port enable is LOW during a clock cycle, the port chip select and write/read select can change states during the setup and hold time window of the cycle. SYNCHRONIZED FIFO FLAGS Each FIFO is synchronized to its port clock through two flip-flop stages. This is done to improve flag reliability by reducing the probability of metastable events on the output when CLKA and CLKB operate asynchronously to one another. EFA, AEA, FFA, and AFA are synchronized to CLKA. EFB, AEB, FFB, and AFB are synchronized to CLKB. Tables 4 and 5 show the relationship of each port flag to FIFO1 and FIFO2. EMPTY FLAGS (EFA EFB EFA, EFB) The empty flag of a FIFO is synchronized to the port clock that reads data from its array. When the empty flag is HIGH, new data can be read to the FIFO output register. When the empty flag is LOW, the FIFO is empty and attempted FIFO reads are ignored. When reading FIFO1 with a byte or word size on port B, EFB is set LOW when the fourth byte or second word of the last long word is read. The read pointer of a FIFO is incremented each time a new word is clocked to the output register. The state machine that controls an empty flag monitors a write-pointer and readpointer comparator that indicates when the FIFO SRAM status is empty, empty+1, or empty+2. A word written to a FIFO can be read to the FIFO output register in a minimum of three cycles of the empty flag synchronizing clock. Therefore, an empty flag is LOW if a word in memory is the next data to be sent to the FIFO output register and two cycles of the port
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IDT723614 CMOS SyncBiFIFOTM WITH BUS MATCHING AND BYTE SWAPPING 64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
clock that reads data from the FIFO have not elapsed since the time the word was written. The empty flag of the FIFO is set HIGH by the second LOW-to-HIGH transition of the synchronizing clock, and the new data word can be read to the FIFO output register in the following cycle. A LOW-to-HIGH transition on an empty flag synchronizing clock begins the first synchronization cycle of a write if the clock transition occurs at time tSKEW1 or greater after the write. Otherwise, the subsequent clock cycle can be the first synchronization cycle (see Figure 13 and 14).
TABLE 1: FLAG PROGRAMMING
FS1 H H L L
FS0 H L H L
RST

ALMOST-FULL AND ALMOST-EMPTY FLAG OFFSET REGISTER (X) 16 12 8 4
FULL FLAG (FFA FFB FFA, FFB) The full flag of a FIFO is synchronized to the port clock that writes data to its array. When the full flag is HIGH, a memory location is free in the SRAM to receive new data. No memory locations are free when the full flag is LOW and attempted writes to the FIFO are ignored. Each time a word is written to a FIFO, the write pointer is incremented. The state machine that controls a full flag monitors a write-pointer and read-pointer comparator that indicates when the FIFO SRAM status is full, full-1, or full-2. From the time a word is read from a FIFO, the previous memory location is ready to be written in a minimum of three cycles of the full flag synchronizing clock. Therefore, a full flag is LOW if less than two cycles of the full flag synchronizing clock have elapsed since the next memory write location has been read. The second LOW-to-HIGH transition on the full flag synchronization clock after the read sets the full flag HIGH and the data can be written in the following clock cycle. A LOW-to-HIGH transition on a full flag synchronizing clock begins the first synchronization cycle of a read if the clock transition occurs at time tSKEW1 or greater after the read. Otherwise, the subsequent clock cycle can be the first synchronization cycle (see Figure 15 and 16).
TABLE 2: PORT-A ENABLE FUNCTION TABLE
CSA
H L L L L L L L
W/RA R X H H H L L L L
ENA X L H H L H L H
MBA X X L H L L H H
CLKA X X X X
A0-A35 Outputs In High-Impedance State In High-Impedance State In High-Impedance State In High-Impedance State Active, FIFO2 Output Register Active, FIFO2 Output Register Active, Mail2 Register Active, Mail2 Register
Port Functions None None FIFO1 Write Mail1 Write None FIFO2 Read None Mail2 Read (Set MBF2 HIGH)
TABLE 3: PORT-B ENABLE FUNCTION TABLE
CSB
H L L L L L L L
W/RB R X H H H L L L L
ENB X L H H L H L H
SIZ1, SIZ0 X X One, both LOW Both HIGH One, both LOW One, both LOW Both HIGH Both HIGH
CLKB X X X X
B0-B35 Outputs In High-Impedance State In High-Impedance State In High-Impedance State In High-Impedance State Active, FIFO1 Output Register Active, FIFO1 Output Register Active, Mail1 Register Active, Mail1 Register
Port Functions None None FIFO2 Write Mail2 Write None FIFO1 read None Mail1 Read (Set MBF1 HIGH)
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IDT723614 CMOS SyncBiFIFOTM WITH BUS MATCHING AND BYTE SWAPPING 64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
ALMOST EMPTY FLAGS (AEA AEB AEA, AEB) The almost-empty flag of a FIFO is synchronized to the port clock that reads data from its array. The state machine that controls an almost-empty flag monitors a write-pointer and a read-pointer comparator that indicates when the FIFO SRAM status is almost empty, almost empty+1, or almost empty+2. The almost-empty state is defined by the value of the almost-full and almost-empty offset register (X). This register is loaded with one of four preset values during a device reset (see Reset above). An almost-empty flag is LOW when the FIFO contains X or less long words in memory and is HIGH when the FIFO contains (X+1) or more long words. Two LOW-to-HIGH transitions of the almost-empty flag synchronizing clock are required after a FIFO write for the almost-empty flag to reflect the new level of fill. Therefore, the almost-empty flag of a FIFO containing (X+1) or more long words remains LOW if two cycles of the synchronizing clock have not elapsed since the write that filled the memory to the (X+1) level. An almost-empty flag is set HIGH by the second LOW-to-HIGH transition of the synchronizing clock after the FIFO write that fills memory to the (X+1) level. A LOW-toHIGH transition of an almost-empty flag synchronizing clock begins the first synchronization cycle if it occurs at time tSKEW2 or greater after the write that fills the FIFO to (X+1) long words. Otherwise, the subsequent synchronizing clock cycle can be the first synchronization cycle (see Figure 17 and 18). ALMOST FULL FLAGS (AFA AFB AFA, AFB) The almost-full flag of a FIFO is synchronized to the port clock that writes data to its array. The state machine that controls an almost-full flag monitors a write-pointer and readpointer comparator that indicates when the FIFO SRAM status is almost full, almost full-1, or almost full-2. The almostfull state is defined by the value of the almost-full and almostempty offset register (X). This register is loaded with one of four preset values during a device reset (see Reset above). An almost-full flag is LOW when the FIFO contains (64-X) or
more long words in memory and is HIGH when the FIFO contains [64-(X+1)] or less long words. Two LOW-to-HIGH transitions of the almost-full flag synchronizing clock are required after a FIFO read for the almost-full flag to reflect the new level of fill. Therefore, the almost-full flag of a FIFO containing [64-(X+1)] or less words remains LOW if two cycles of the synchronizing clock have not elapsed since the read that reduced the number of long words in memory to [64-(X+1)]. An almost-full flag is set HIGH by the second LOW-to-HIGH transition of the synchronizing clock after the FIFO read that reduces the number of long words in memory to [64-(X+1)]. A LOW-to-HIGH transition of an almost-full flag synchronizing clock begins the first synchronization cycle if it occurs at time tSKEW2 or greater after the read that reduces the number of long words in memory to [64(X+1)]. Otherwise, the subsequent synchronizing clock cycle can be the first synchronization cycle (see Figure 19 and 20). MAILBOX REGISTERS Each FIFO has a 36-bit bypass register to pass command and control information between port A and port B without putting it in queue. The mailbox-select (MBA, MBB) inputs choose between a mail register and a FIFO for a port data transfer operation. A LOW-to-HIGH transition on CLKA writes A0-A35 data to the mail1 register when a port A write is selected by CSA, W/RA, and ENA with MBA HIGH. A LOWto-HIGH transition on CLKB writes B0-B35 data to the mail2 register when a port B write is selected by CSB, W/RB, and ENB with both SIZ1 and SIZ0 HIGH. Writing data to a mail register sets the corresponding flag (MBF1 or MBF2) LOW. Attempted writes to a mail register are ignored while the mail flag is LOW. When the port A data outputs (A0-A35) are active, the data on the bus comes from the FIFO2 output register when MBA is LOW and from the mail2 register when MBA is HIGH. When the port B data outputs (B0-B35) are active, the data on the bus comes from the FIFO1 output register when either one
TABLE 4: FIFO1 FLAG OPERATION Synchronized Number of 36-Bit Words in the FIFO1(1) 0 1 to X (X+1) to [64-(X+1)] (64-X) to 63 64 to CLKB Synchronized to CLKA
TABLE 5: FIFO2 FLAG OPERATION Synchronized Number of 36-Bit Words in the FIFO2(1) 0 1 to X (X+1) to [64-(X+1)] (64-X) to 63 64 to CLKA Synchronized to CLKB
EFB
L H H H H
AEB
L L H H H
AFA
H H H L L
FFA
H H H H L
EFA
L H H H H
AEA
L L H H H
AFB
H H H L L
FFB
H H H H L
NOTE: 1. X is the value in the almost-empty flag and almost-full flag offset register.
8
IDT723614 CMOS SyncBiFIFOTM WITH BUS MATCHING AND BYTE SWAPPING 64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR TEMPERATURE RANGE (UNLESS OTHERWISE NOTED)(1)
Symbol VCC VI
(2) (2)
Rating Supply Voltage Range Input Voltage Range Output Voltage Range Input Clamp Current, (VI < 0 or VI > VCC) Output Clamp Current, (VO < 0 or VO > VCC) Continuous Output Current, (VO = 0 to VCC) Continuous Current Through VCC or GND Operating Free Air Temperature Range Storage Temperature Range
Commercial -0.5 to 7 -0.5 to VCC+0.5 -0.5 to VCC+0.5 20 50 50 500 0 to 70 -65 to 150
Unit V V V mA mA mA mA C C
VO
IIK IOK IOUT ICC TA TSTG
NOTES: 1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "Recommended Operating Conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VIH VIL IOH IOL TA Parameter Supply Voltage HIGH Level Input Voltage LOW-Level Input Voltage HIGH-Level Output Current LOW-Level Output Current Operating Free-air Temperature Min. 4.5 2 - - - 0 Max. Unit 5.5 - 0.8 -4 8 70 V V V mA mA C
ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING FREE-AIR TEMPERATURE RANGE (UNLESS OTHERWISE NOTED)
Parameter VOH VOL II IOZ ICC CIN COUT VCC = 4.5V, VCC = 4.5 V, VCC = 5.5 V, VCC = 5.5 V, VCC = 5.5 V, VI = 0, VO = 0, Test Conditions IOH = -4 mA IOL = 8 mA VI = VCC or 0 VO = VCC or 0 IO = 0 mA, f = 1 MHz f = 1 MHZ VI = VCC or GND 4 8 Min. 2.4 0.5 50 50 1 Typ.(1) Max. Unit V V A A mA pF pF
NOTE: 1 . All typical values are at VCC = 5 V, TA = 25C.
9
IDT723614 CMOS SyncBiFIFOTM WITH BUS MATCHING AND BYTE SWAPPING 64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE (See Figures 4 through 26)
Symbol fS tCLK tCLKH tCLKL tDS tENS tSZS tSWS tPGS tRSTS tFSS tDH tENH tSZH tSWH tPGH tRSTH tFSH tSKEW1
(3)
Parameter Clock Frequency, CLKA or CLKB Clock Cycle Time, CLKA or CLKB Pulse Duration, CLKA and CLKB HIGH Pulse Duration, CLKA and CLKB LOW Setup Time, A0-A35 before CLKA and B0-B35 before CLKB Setup Time, CSA, W/RA, ENA and MBA before CLKA; CSB,W/RB and ENB before CLKB Setup Time, SIZ0, SIZ1,and BE before CLKB Setup Time, SW0 and SW1 before CLKB Setup Time, ODD/EVEN and PGA before CLKA; ODD/EVEN and PGB before CLKB Setup Time, RST LOW before CLKA or CLKB(2) Setup Time, FS0 and FS1 before RST HIGH Hold Time, A0-A35 after CLKA and B0-B35 after CLKB Hold Time, CSA, W/RA, ENA and MBA after CLKA; CSB, W/RB, and ENB after CLKB Hold Time, SIZ0, SIZ1, and BE after CLKB Hold Time, SW0 and SW1 after CLKB Hold Time, ODD/EVEN and PGA after CLKA; ODD/EVEN and PGB after CLKB(1) Hold Time, RST LOW after CLKA or CLKB(2) Hold Time, FS0 and FS1 after RST HIGH Skew Time, between CLKA and CLKB for EFA, EFB, FFA, and FFB
(1)
IDT723614L15 IDT723614L20 IDT723614L30 Min. Max. Min. Max. Min. Max. - 15 6 6 4 5 4 5 4 5 5 1 1 2 0 0 5 4 8 9 66.7 - - - - - - - - - - - - - - - - - - - - 20 8 8 5 5 5 7 5 6 6 1 1 2 0 0 6 4 8 16 50 - - - - - - - - - - - - - - - - - - - - 30 12 12 6 6 6 8 6 7 7 1 1 2 0 0 7 4 10 20 33.4 - - - - - - - - - - - - - - - - - - -
Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tSKEW2(3) Skew Time, between CLKA and CLKB for AEA, AEB, AFA, and AFB
NOTES: 1. Only applies for a clock edge that does a FIFO read. 2. Requirement to count the clock edge as one of at least four needed to reset a FIFO. 3. Skew time is not a timimg constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle.
10
IDT723614 CMOS SyncBiFIFOTM WITH BUS MATCHING AND BYTE SWAPPING 64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE, CL = 30pF (See Figures 4 through 26)
IDT723614L15 IDT723614L20 IDT723614L30 Min. Max. Min. Max. Min. Max. 2 2 2 2 2 1 10 10 10 10 10 9 2 2 2 2 2 1 12 12 12 12 12 12 2 2 2 2 2 1 15 15 15 15 15 15
Symbol tA tWFF tREF tPAE tPAF tPMF
Parameter Access Time, CLKA to A0-A35 and CLKB to B0-B35 Propagation Delay Time, CLKA to FFA and CLKB to FFB
Unit ns ns ns ns ns ns
Propagation Delay Time, CLKA to EFA and and CLKB to EFB
Propagation Delay Time, CLKA to AEA and CLKB to AEB Propagation Delay Time, CLKA to AFA and CLKB to AFB
Propagation Delay Time, CLKA to MBF1 LOW or MBF2 HIGH and CLKB to MBF2 LOW or MBF1 HIGH Propagation Delay Time, CLKA to B0-B35(1) and CLKB to A0-A35(2) Propagation delay time, CLKB to PEFB Propagation Delay Time, MBA to A0-A35 valid and SIZ1, SIZ0 to B0-B35 valid Propagation Delay Time, A0-A35 valid to PEFA valid; B0-B35 valid to PEFB valid
tPMR tPPE(3) tMDV tPDPE tPOPE tPOPB(4)
3 2 1 3 3 2
11 11 11 10 11 11
3 2 1 3 3 2
13 12 11. 5 11 12 12
3 2 1 3 3 2
15 13 12 13 14 14
ns ns ns ns ns ns
Propagation Delay Time, ODD/EVEN to PEFA and PEFB
Propagation Delay Time, ODD/EVEN to parity bits (A8, A17, A26, A35) and (B8, B17, B26, B35) Propagation Delay Time, CSA, ENA,W/RA, MBA, or PGA to PEFA; CSB, ENB, W/RB, SIZ1, SIZ0, or PGB to PEFB Propagation Delay Time, CSA, ENA, W/RA, MBA, or PGA to parity bits (A8, A17, A26, A35); CSB, ENB, W/RB,SIZ1, SIZ0, or PGB to parity bits (B8, B17, B26, B35) Propagation Delay Time, RST to (MBF1, MBF2) HIGH Enable Time, CSA and W/RA LOW to A0-A35 active and CSB LOW and W/RB HIGH to B0-B35 active Disable Time, CSA or W/RA HIGH to A0-A35 at high impedance and CSB HIGH or W/RB LOW to B0-B35 at high impedance
tPEPE
1
11
1
12
1
14
ns
tPEPB(4)
3
12
3
13
3
14
ns
tRSF tEN
1 2
15 10
1 2
20 12
1 2
30 14
ns ns
tDIS
1
8
1
9
1
11
ns
NOTES: 1. Writing data to the mail1 register when the B0-B35 outputs are active and SIZ1, SIZ0 are HIGH. 2. Writing data to the mail2 register when the A0-A35 outputs are active and MBA is HIGH. 3. Only applies when a new port B bus size is implemented by the rising CLKB edge. 4. Only applies when reading data from a mail register.
11
IDT723614 CMOS SyncBiFIFOTM WITH BUS MATCHING AND BYTE SWAPPING 64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
A35--A27
BYTE ORDER ON PORT A:
A26--A18
A17--A9
A8--A0
A
B35--B27
B
B26--B18
C
B17--B9
D
B8--B0
Write to FIFO1/ Read From FIFO2
BE
X
SIZ1 L
SIZ0 L
A
B
C
D
Read from FIFO1/ Write to FIFO2
(a) LONG WORD SIZE
B35--B27
B26--B18
B17--B9
B8--B0 1st: Read from FIFO1/ Write to FIFO2
BE
L
SIZ1 L
SIZ0 H
A
B35--B27
B
B26--B18 B17--B9 B8--B0
C
D
(b) WORD SIZE -- BIG ENDIAN
2nd: Read from FIFO1/ Write to FIFO2
BE
H
SIZ1 L
SIZ0 H
B35--B27
B26--B18
B17--B9
B8--B0
C
B35--B27 B26--B18 B17--B9
D
B8--B0
1st: Read from FIFO1/ Write to FIFO2
A
(c) WORD SIZE -- LITTLE ENDIAN
B
2nd: Read from FIFO1/ Write to FIFO2
BE
L
B35--B27 SIZ1 H SIZ0 L
B26--B18
B17--B9
B8--B0 1st: Read from FIFO1/ Write to FIFO2
A
B35--B27 B26--B18 B17--B9 B8--B0
B
B35--B27 B26--B18 B17--B9 B8--B0
2nd: Read from FIFO1/ Write to FIFO2
C
B35--B27 B26--B18 B17--B9 B8--B0
3rd: Read from FIFO1/ Write to FIFO2
D
(d) BYTE SIZE -- BIG ENDIAN
4th: Read from FIFO1/ Write to FIFO2
3146 drw fig 01
Figure 1. Dynamic Bus Sizing
12
IDT723614 CMOS SyncBiFIFOTM WITH BUS MATCHING AND BYTE SWAPPING 64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
BE
H
SIZ1 H
SIZ0 L
B35--B27
B26--B18
B17--B9
B8--B0
D
B35--B27 B26--B18 B17--B9 B8--B0
1st: Read from FIFO1/ Write to FIFO2
C
B35--B27 B26--B18 B17--B9 B8--B0
2nd: Read from FIFO1/ Write to FIFO2
B
B35--B27 B26--B18 B17--B9 B8--B0
3rd: Read from FIFO1/ Write to FIFO2
A
(d) BYTE SIZE -- LITTLE ENDIAN
4th: Read from FIFO1/ Write to FIFO2
3146 drw fig 01a
Figure 1. Dynamic Bus Sizing (continued) DESCRIPTION (CONTINUED) or both SIZ1 and SIZ0 are LOW and from the mail2 register when both SIZ1 and SIZ0 are HIGH.The mail1 register flag (MBF1) is set HIGH by a rising CLKB edge when a port B read is selected by CSB, W/RB, and ENB with both SIZ1 and SIZ0 HIGH. The mail2 register flag (MBF2) is set HIGH by a LOWto-HIGH transition on CLKA when port A read is selected by CSA, W/RA, and ENA and MBA is HIGH. The data in the mail register remains intact after it is read and changes only when new data is written to the register. DYNAMIC BUS SIZING The port B bus can be configured in a 36-bit long word, 18-bit word, or 9-bit byte format for data read from FIFO1 or written to FIFO2. Word- and byte-size bus selections can utilize the most significant bytes of the bus (big endian) or least significant bytes of the bus (little endian). Port B bus size can be changed dynamically and synchronous to CLKB to communicate with peripherals of various bus widths. The levels applied to the port B bus size select (SIZ0, SIZ1) inputs and the big-endian select (BE) input are stored on each CLKB LOW-to-HIGH transition. The stored port B bus size selection is implemented by the next rising edge on CLKB according to Figure 1. Only 36-bit long-word data is written to or read from the two FIFO memories on the IDT723614. Bus-matching operations are done after data is read from the FIFO1 RAM and before data is written to the FIFO2 RAM. Port B bus sizing does not apply to mail register operations. BUS-MATCHING FIFO1 READS Data is read from the FIFO1 RAM in 36-bit long word increments. If a long word bus size is implemented, the entire long word immediately shifts to the FIFO1 output register. If byte or word size is implemented on port B, only the first one or two bytes appear on the selected portion of the FIFO1 output register, with the rest of the long word stored in auxiliary registers. In this case, subsequent FIFO1 reads with the same bus-size implementation output the rest of the long word to the FIFO1 output register in the order shown by Figure1. Each FIFO1 read with a new bus-size implementation automatically unloads data from the FIFO1 RAM to its output register and auxiliary registers. Therefore, implementing a new port B bus size and performing a FIFO1 read before all bytes or words stored in the auxiliary registers have been read results in a loss of the unread long word data. When reading data from FIFO1 in byte or word format, the unused B0-B35 outputs remain inactive but static, with the unused FIFO1 output register bits holding the last data value to decrease power consumption. BUS-MATCHING FIFO2 WRITES Data is written to the FIFO2 RAM in 36-bit long word increments. FIFO2 writes, with a long-word bus size, immediately store each long word in FIFO2 RAM. Data written to FIFO2 with a byte or word bus size stores the initial bytes or words in auxiliary registers. The CLKB rising edge that writes the fourth byte or the second word of long word to FIFO2 also stores the entire long word in FIFO2 RAM. The bytes are arranged in the manner shown in Figure 1. Each FIFO2 write with a new bus-size implementation resets the state machine that controls the data flow from the auxiliary registers to the FIFO2 RAM. Therefore, implementing a new bus size and performing a FIFO2 write before bytes or words stored in the auxiliary registers have been loaded to FIFO2 RAM results in a loss of data.
13
IDT723614 CMOS SyncBiFIFOTM WITH BUS MATCHING AND BYTE SWAPPING 64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
PORT-B MAIL REGISTER ACCESS In addition to selecting port-B bus sizes for FIFO reads and writes, the port B bus size select (SIZ0, SIZ1) inputs also access the mail registers. When both SIZ0 and SIZ1 are HIGH, the mail1 register is accessed for a port B long word read and the mail2 register is accessed for a port B long word write. The mail register is accessed immediately and any bussizing operation that may be underway is unaffected by the mail register access. After the mail register access is complete, the previous FIFO access can resume in the next CLKB cycle. The logic diagram in Figure 2 shows the previous bussize selection is preserved when the mail registers are accessed from port B. A port B bus size is implemented on each rising CLKB edge according to the states of SIZ0_Q, SIZ1_Q,
word read from FIFO1 or written to FIFO2 is maintained until the entire long word is transferred, regardless of the SW0 and SW1 states during subsequent writes or reads. Figure 3 is an example of the byte-order swapping available for long words. Performing a byte swap and bus size simultaneously for a FIFO1 read first rearranges the bytes as shown in Figure 3, then outputs the bytes as shown in Figure 1. Simultaneous bus-sizing and byte-swapping operations for FIFO2 writes, first loads the data according to Figure 1, then swaps the bytes as shown in Figure 3 when the long word is loaded to FIFO2 RAM.
and BE_Q.
BYTE SWAPPING The byte-order arrangement of data read from FIFO1 or data written to FIFO2 can be changed synchronous to the rising edge of CLKB. Byte-order swapping is not available for mail register data. Four modes of byte-order swapping (including no swap) can be done with any data port size selection. The order of the bytes are rearranged within the long word, but the bit order within the bytes remains constant. Byte arrangement is chosen by the port B swap select (SW0, SW1) inputs on a CLKB rising edge that reads a new long word from FIFO1 or writes a new long word to FIFO2. The byte order chosen on the first byte or first word of a new long
PARITY CHECKING The port A inputs (A0-A35) and port B inputs (B0-B35) each have four parity trees to check the parity of incoming (or outgoing) data. A parity failure on one or more bytes of the port A data bus is reported by a LOW level on the port parity error flag (PEFA). A parity failure on one or more bytes of the port B data input that are valid for the bus-size implementation is reported by a LOW level on the port B parity error flag (PEFB).Odd or even parity checking can be selected, and the parity error flags can be ignored if this feature is not desired. Parity status is checked on each input bus according to the level of the odd/even parity (ODD/EVEN) select input. A parity error on one or more valid bytes of a port is reported by a LOW level on the corresponding port parity error flag (PEFA, PEFB) output. Port A bytes are arranged as A0-A8, A9-A17,
CLKB
G1 1 SIZ0 SIZ1
MUX
BE
**
1
D
Q
*
*
*
SIZ0 Q SIZ1 Q BE Q
3146 drw fig 02
Figure 2. Logic Diagrams for SIZ0, SIZ1, and BE Register
14
IDT723614 CMOS SyncBiFIFOTM WITH BUS MATCHING AND BYTE SWAPPING 64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
A35--A27 SW1 L L SW0 L L
A26--A18
A17--A9
A8--A0
A
B
C
D
A
B35--B27
B
B26--B18
(a) NO SWAP
C
B17--B9
D
B8--B0
A35--A27 SW1 L SW0 H
A26--A18
A17--A9
A8--A0
A
B
C
D
D
B35--B27
C
B26--B18
(b) BYTE SWAP
B
B17--B9
A
B8--B0
A35--A27 SW1 H SW0 L
A26--A18
A17--A9
A8--A0
A
B
C
D
C
B35--B27
D
B26--B18
(c) WORD SWAP
A
B17--B9
B
B8--B0
A35--A27 SW1 H SW0 H
A26--A18
A17--A9
A8--A0
A
B
C
D
B
B35--B27
A
B26--B18
D
B17--B9
C
B8--B0
(d) BYTE-WORD SWAP
3146 drw fig 03
Figure 3. Byte Swapping (Long Word Size Example)
15
IDT723614 CMOS SyncBiFIFOTM WITH BUS MATCHING AND BYTE SWAPPING 64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
A18-A26, and A27-A35. Port B bytes are arranged as B0-B8, B9-B17, B18-B26, and B27-B35, and its valid bytes are those used in a port B bus-size implementation. When odd/even parity is selected, a port parity error flag (PEFA, PEFB) is LOW if any byte on the port has an odd/even number of LOW levels applied to the bits. The four parity trees used to check the A0-A35 inputs are shared by the mail2 register when parity generation is selected for port A reads (PGA = HIGH). When a port A read from the mail2 register with parity generation is selected with CSA LOW, ENA HIGH, W/RA LOW, MBA HIGH, and PGA HIGH, the port A parity error flag (PEFA) is held HIGH regardless of the levels applied to the A0-A35 inputs. Likewise, the parity trees used to check the B0-B35 inputs are shared by the mail1 register when parity generation is selected for port B reads (PGB = HIGH). When a port B read from the mail1 register with parity generation is selected with CSB LOW, ENB HIGH, W/ RB LOW, both SIZ0 and SIZ1 HIGH, and PGB HIGH, the port B parity error flag (PEFB) is held HIGH regardless of the levels applied to the B0-B35 inputs. PARITY GENERATION A HIGH level on the port A parity generate select (PGA) or port B parity generate select (PGB) enables the IDT723614 to generate parity bits for port reads from a FIFO or mailbox register. Port A bytes are arranged as A0-A8, A9-A17, A1826, and A27-A35, with the most significant bit of each byte used as the parity bit. Port B bytes are arranged as B0-B8, B9B17, B18-B26, and B27-B35, with the most significant bit of
each byte used as the parity bit. A write to a FIFO or mail register stores the levels applied to all nine inputs of a byte regardless of the state of the parity generate select (PGA, PGB) inputs. When data is read from a port with parity generation selected, the lower eight bits of each byte are used to generate a parity bit according to the level on the ODD/ EVEN select. The generated parity bits are substituted for the levels originally written to the most significant bits of each byte as the word is read to the data outputs. Parity bits for FIFO data are generated after the data is read from SRAM and before the data is written to the output register. Therefore, the port A parity generate select (PGA) and odd/even parity select (ODD/EVEN) have setup and hold time constraints to the port A clock (CLKA) and the port B parity generate select (PGB) and ODD/EVEN have setup and hold-time constraints to the port B clock (CLKB). These timing constraints only apply for a rising clock edge used to read a new long word to the FIFO output register. The circuit used to generate parity for the mail1 data is shared by the port B bus (B0-B35) to check parity and the circuit used to generate parity for the mail2 data is shared by the port A bus (A0-A35) to check parity. The shared parity trees of a port are used to generate parity bits for the data in a mail register when the port chip select (CSA, CSB) is LOW, enable (ENA, ENB) is HIGH, write/read select (W/RA, W/RB) input is LOW, the mail register is selected (MBA is HIGH for port A; both SIZ0 and SIZ1 are HIGH for port B), and port parity generate select (PGA, PGB) is HIGH. Generating parity for mail register data does not change the contents of the register.
16
IDT723614 CMOS SyncBiFIFOTM WITH BUS MATCHING AND BYTE SWAPPING 64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
CLKA tRSTH CLKB tRSTS tFSS tFSH
RST
FS1,FS0 0,1 tWFF tWFF
FFA EFA FFB EFB MBF1, MBF2 AEA AFA AEB AFB
tRSF
tREF tWFF
tWFF
tREF
tPAE
tPAF tPAE
tPAF
3146 drw 04
Figure 4. Device Reset Loading the X Register with the Value of Eight
17
IDT723614 CMOS SyncBiFIFOTM WITH BUS MATCHING AND BYTE SWAPPING 64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
tCLK tCLKH CLKA tCLKL
FFA CSA
HIGH tENS tENS tENH tENH
W/RA tENS MBA tENS ENA tDS A0 - A35 ODD/ tPDPE Valid tPDPE Valid
3146 drw 05
tENH
tENH tDH W1(1)
tENS
tENH
tENS
tENH
W2(1)
No Operation
EVEN PEFA
NOTE: 1. Written to FIFO1.
Figure 5. Port-A Write Cycle Timing for FIFO1
18
IDT723614 CMOS SyncBiFIFOTM WITH BUS MATCHING AND BYTE SWAPPING 64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
CLKB
FFB CSB
W/RB
HIGH t ENS t ENS t ENS tENH tSWH tENS tENH
ENB tSWS SW1, SW0
BE
SIZ1, SIZ0 B0-B35 ODD/
tSZS tSZS (0,0)
tSZH tSZH (0,0) tDS tDH NOT (1,1)(1)
EVEN PEFB
tPPE VALID
tPDPE VALID
3146 drw 06
NOTE: 1. SIZ0 = HIGH and SIZ1 = HIGH writes data to the mail2 register
DATA SWAP TABLE FOR LONG-WORD WRITES TO FIFO2 SWAP MODE SW1 L L H H SW0 L H L H B35-27 A D C B DATA WRITTEN TO FIFO2 B26-18 B C D A B17-B9 C B A D B8-B0 D A B C A35-27 A A A A DATA READ FROM FIFO2 A26-A18 B B B B A17-A9 C C C C A8-A0 D D D D
Figure 6. Port-B Long-Word Write Cycle Timing for FIFO2
19
IDT723614 CMOS SyncBiFIFOTM WITH BUS MATCHING AND BYTE SWAPPING 64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
CLKB
FFB CSB
W/RB
HIGH tENS tENS tENS tENH tSWH tSZH tSZH
(0, 1) NOT (1,1) (1)
tENH
tENS
tENH
ENB tSWS SW1, SW0 tSZS tSZS tSZS tDS B0-B17 tDS tDH
BE
tSZS SIZ1, SIZ0 Little Endian
(0, 1)
tSZH tSZH
tDH
Big Endian B18-B35 ODD/EVEN
PEFB
tPPE VALID
tPDPE VALID
3146 drw 07
NOTES: 1. SIZ0 = HIGH and SIZ1 = HIGH writes data to the mail2 register. 2. PEFB indicates parity error for the following bytes: B35-B27 and B26-B18 for big-endian bus, and B17-B9 and B-8-B0 for little-endian bus.
DATA SWAP TABLE FOR WORD WRITES TO FIFO2 SWAP MODE SW1 SW0 L L 1 2 L H 1 2 H L 1 2 H H 1 2 WRITE NO. DATA WRITTEN TO FIFO2 BIG ENDIAN B35-27 A C D B C A B D B26-18 B D C A D B A C LITTLE ENDIAN B17-B9 C A B D A C D B B8-B0 D B A C B D C A A B C D A B C D A B C D A35-27 A A26-A18 B A17-A9 C A8-A0 D DATA READ FROM FIFO2
Figure 7. Port-B Word Write Cycle Timing for FIFO2
20
IDT723614 CMOS SyncBiFIFOTM WITH BUS MATCHING AND BYTE SWAPPING 64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
CLKB
FFB CSB
HIGH tENS tENH
tENS W/RB tENS ENB tSWS SW1, SW0 tSZS tSZS SIZ1, SIZ0 Little Endian Big Endian B0B8 B27B35 (1,0) tDS tDS tSZH tSZS tSZH tSZS (1,0) tDH tDH tENH tSZH tSZH (1,0) (1,0) Not (1,1)(1) tENH tENS tENH
BE
ODD/EVEN tPPE tPDPE Valid Valid
3146 drw 08
tPDPE Valid
tPDPE Valid
PEFB
NOTES: 1. SIZ0 = HIGH amd SIZ1 = HIGH writes data to the mail2 register. 2. PEFB indicates parity error for the following bytes: B35--B27 for big-endian bus and B17--B9 for little-endian bus.
Figure 8. Port-B Byte Write Cycle Timing for FIFO2
21
IDT723614 CMOS SyncBiFIFOTM WITH BUS MATCHING AND BYTE SWAPPING 64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
DATA SWAP TABLE FOR BYTE WRITES TO FIFO2 DATA WRITTEN TO FIFO2 BIG LITTLE ENDIAN ENDIAN B35-B27 1 2 L L 3 4 1 L H 2 3 4 1 H L 2 3 4 1 H H 2 3 4 A B C D D C B A C D A B B A D C B8-80 D C B A A B C D B A D C C D A B A B C D A B C D A B C D A B C D A35-A27
SWAP MODE SW1 SW0
WRITE NO.
DATA READ FROM FIFO2 A26-A18 A17-A9 A8-A0
Figure 8. Port-B Byte Write Cycle Timing for FIFO2 (continued)
22
IDT723614 CMOS SyncBiFIFOTM WITH BUS MATCHING AND BYTE SWAPPING 64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
CLKB
EFB CSB
W/RB
HIGH
tENS ENB tSWS SW1, SW0 tSZS tSZS SIZ1, SIZ0 PGB, ODD/ (0,0)
tENH tSWH
tENS No Operation
tENH
BE
tSZH tSZH NOT (1,1)(1) tPGS tEN (0,0) tPGH tA Previous Data tA W1
(2)
NOT (1,1)(1)
EVEN
tDIS W2 (2)
3146 drw 09
B0-B35
NOTES: 1. SIZ0 = HIGH and SIZ1 = HIGH selects the mail1 register for output on B0-B35. 2. Data read from FIFO1.
DATA SWAP TABLE FOR FIFO LONG-WORD READS FROM FIFO1
DATA WRITTEN TO FIFO1 A35-A27 A A A A A26-A18 B B B B A17-A9 C C C C A8-A0 D D D D
SWAP MODE SW1 L L H H SW0 L H L H
DATA READ FROM FIFO1 B35-B27 B26-B18 A D C B B C D A B17-B9 C B A D B8-B0 D A B C
Figure 9. Port-B Long-Word Read Cycle Timing for FIFO1
23
IDT723614 CMOS SyncBiFIFOTM WITH BUS MATCHING AND BYTE SWAPPING 64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
CLKB
EFB CSB
W/RB
HIGH
tENS ENB tSWS SW1, SW0 tSZS tSZS SIZ1, SIZ0 PGB, ODD/ (0,1)
tENH tSWH No Operation
BE
tSZH tSZH NOT (1,1)(1) tPGS tEN (0,1) tPGH tA Previous Data tA Previous Data tA Read 1 tA Read 1 tDIS Read 2 tDIS Read 2
3146 drw 10
NOT (1,1)(1)
EVEN
Little Endian(2) Big Endian(2)
B0-B17 B18-B35
NOTES: 1. SIZ0 = HIGH and SIZ1 = HIGH selects the mail1 register for output on B0-B35. 2. Unused word B0-B17 or B18-B35 holds last FIFO1 output register data for word-size reads.
DATA SWAP TABLE FOR WORD READS FROM FIFO1 DATA READ FROM FIFO1 DATA WRITTEN TO FIFO1 A35-A27 A A26-A18 B A17-A9 C A8-A0 D SWAP MODE SW1 L SW0 L 1 2 1 2 1 2 1 2 READ NO. BIG ENDIAN B35-B27 B26-B18 A B C D D B C A B D C A D B A C LITTLE ENDIAN B17-B9 C A B D A C D B B8-B0 D B A C B D C A
A
B
C
D
L
H
A
B
C
D
H
L
A
B
C
D
H
H
Figure 10. Port-B Word Read Cycle Timing for FIFO1
24
IDT723614 CMOS SyncBiFIFOTM WITH BUS MATCHING AND BYTE SWAPPING 64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
CLKB
EFB CSB
W/RB
HIGH
tENS ENB tSWS SW1, SW0 tSZS tSZS SIZ1, SIZ0 PGB, ODD/ (1,0) Not (1,1) tPGS tEN
(1)
tENH tSWH No Operation
BE
tSZH tSZH (1,0) (1,0) Not (1,1)(1) tPGH tA Read 1 tA Read 1 tA Read 2 tA Read 2 tA Read 3 tA Read 3 tDIS Read 4 tDIS Read 4
3146 drw 11
(1,0) Not (1,1) (1)
Not (1,1) (1)
EVEN
B0-B8
tA Previous Data tA
B27-B35
Previous Data
NOTES: 1. SIZ0 = HIGH and SIZ1 = HIGH selects the mail1 register for output on B0-B35. 2. Unused bytes hold last FIFO1 output regisger data for byte-size reads.
DATA SWAP TABLE FOR BYTE READS FROM FIFO1 DATA READ FROM FIFO 1 DATA WRITTEN TO FIFO 1 A35-A27 A26-A18 A17-A9 A8-A0 SWAP MODE SW1 SW0 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 READ NO. BIG ENDIAN B35-B27 A B C D D C B A C D A B B A D C LITTLE ENDIAN B8-B0 D C B A A B C D B A D C C D A B
A
B
C
D
L
L
A
B
C
D
L
H
A
B
C
D
H
L
A
B
C
D
H
H
Figure 11. Port-B Byte Read Cycle Timing for FIFO1
25
IDT723614 CMOS SyncBiFIFOTM WITH BUS MATCHING AND BYTE SWAPPING 64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
tCLK tCLKH CLKA tCLKL
EFA CSA
W/RA
HIGH
MBA tENH tENS ENA tMDV A0 - A35 PGA, ODD/
3146 drw 12
tENS
tENH tENS tA
tENH
tA Previous Data Word 1(1) tPGS
tEN tPGS tPGH
No Operation tDIS Word 2(1)
tPGH
EVEN
NOTE: 1. Read from FIFO2..
Figure 12. Port-A Read Cycle Timing for FIFO2
26
IDT723614 CMOS SyncBiFIFOTM WITH BUS MATCHING AND BYTE SWAPPING 64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
tCLK tCLKH tCLKL CLKA
CSA
WRA MBA
LOW HIGH tENS tENS tENH tENH
ENA
FFA
A0 - A35
HIGH tDS W1
tDH
tSKEW1 CLKB
(1)
tCLK tCLKH tCLKL 1
2 tREF tREF
EFB CSB
W/RB SIZ1, SIZ0 ENB LOW LOW LOW
FIFO1 Empty
tENS
tENH
tA B0 -B35 W1
3146 drw 13
NOTES: 1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for EFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of EFB HIGH may occur one CLKB cycle later than shown. 2. Port-B size of long word is selected for FIFO1 read by SIZ1 = LOW, SIZ0 = LOW. If port-B size is word or byte, EFB is set LOW by the last word or byte read from FIFO1, respectively.
Figure13. EFB Flag Timing and First Data Read when FIFO1 is Empty
27
IDT723614 CMOS SyncBiFIFOTM WITH BUS MATCHING AND BYTE SWAPPING 64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
tCLK tCLKH tCLKL CLKB
CSB
WRB SIZ1, SIZ0 ENB
LOW HIGH tENS tENS tENH tENH
FFB
B0 - B35
HIGH tDS W1
tDH
tSKEW1 CLKA
(1)
tCLK tCLKH tCLKL 1
2 tREF tREF
EFA CSA
W/RA MBA ENA LOW LOW LOW
FIFO2 Empty
tENS
tENH
tA A0 -A35 W1
3146 drw 14
NOTES: 1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for EFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising CLKA edge is less than tSKEW1, then the transition of EFA HIGH may occur one CLKA cycle later than shown. 2. Port B size of long word is selected for FIFO2 write by SIZ1 = LOW, SIZ0 = LOW. If port B size is word or byte tSKEW1 is referenced to the rising CLKB edge that writes the last word or byte of the long word, respectively.
Figure 14. EFA Flag Timing and First Data Read when FIFO2 is Empty
28
IDT723614 CMOS SyncBiFIFOTM WITH BUS MATCHING AND BYTE SWAPPING 64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
tCLK tCLKH CLKB tCLKL
CSB
W/RB SIZ1, SIZ0 ENB
LOW LOW LOW tENS tENH
EFB
B0 - B35
HIGH tA
Previous Word in FIFO1 Output Register Next Word From FIFO1
(1)
tSKEW1 CLKA
tCLK tCLKH 1 tCLKL 2 tWFF tWFF
FFA CSA
WRA MBA
FIFO1 Full LOW HIGH tENS tENS tENH tENH tDH
To FIFO1
3146 drw 15
ENA tDS A0 - A35
NOTES: 1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for FFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising CLKA edge is less than tSKEW1, then FFA may transition HIGH one CLKA cycle later than shown. 2. Port B size of long word is selected for FIFO1 read by SIZ1 = LOW, SIZ0 = LOW. If port B size is word or byte, tSKEW1 is referenced from the rising CLKB edge that reads the last word or byte of the long word, respectively.
Figure 15. FFA Flag Timing and First Available Write when FIFO1 is Full.
29
IDT723614 CMOS SyncBiFIFOTM WITH BUS MATCHING AND BYTE SWAPPING 64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
tCLK tCLKH CLKA tCLKL
CSA
W/RA MBA ENA
LOW LOW LOW tENS tENH
EFA
A0 - A35
HIGH tA
Previous Word in FIFO2 Output Register Next Word From FIFO2
(1)
tSKEW1 CLKB
tCLK tCLKH 1 tCLKL 2 tWFF tWFF
FFB CSB
WRB SIZ1, SIZ0 ENB
FIFO2 Full LOW HIGH tENS tENS tDS tENH tENH tDH
To FIFO2
3146 drw 16
B0 - B35
NOTES: 1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for FFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW1, then FFB may transition HIGH one CLKB cycle later than shown. 2. Port B size of long word is selected for FIFO2 write by SIZ1 = LOW, SIZ0 = LOW. If port B size is word or byte, FFB is set LOW by the last word or byte write of the long word, respectively.
Figure 16. FFB Flag Timing and First Available Write when FIFO2 is Full
30
IDT723614 CMOS SyncBiFIFOTM WITH BUS MATCHING AND BYTE SWAPPING 64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
CLKA tENS ENA tSKEW2 CLKB
(1)
tENH
1
2 tPAE tPAE
(X+1) Long Words in FIFO1
AEB
ENB
X Long Word in FIFO1
tENS
tENH
3146 drw 17
NOTES: 1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AEB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW2, then AEB may transition HIGH one CLKB cycle later than shown. 2. FIFO1 Write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = LOW, MBB = LOW). 3. Port B size of long word is selected for FIFO1 read by SIZ1 = LOW, SIZ0 = LOW. If port B size is word or byte, AEB is set LOW by the last word or byte read of the long word, respectively.
Figure 17. Timing for AEB when FIFO1 is Almost Empty
CLKB tENS ENB tSKEW2 CLKA
(1)
tENH
1
2 tPAE tPAE
(X+1) Long Words in FIFO2
AEA
ENA
X Long Words in FIFO2
tENS
tENH
3146 drw 18
NOTES: 1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AEA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising CLKA edge is less than tSKEW2, then AEA may transition HIGH one CLKA cycle later than shown. 2. FIFO2 Write (CSB = LOW, W/RB = HIGH, MBB = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW). 3. Port B size of long word is selected for FIFO2 write by SIZ1 = LOW, SIZ0 = LOW. If port B size is word or byte, tSKEW2 is referenced from the rising CLKB edge that writes the last word or byte of the long word, respectively.
Figure 18. Timing for AEA when FIFO2 is Almost Empty
31
IDT723614 CMOS SyncBiFIFOTM WITH BUS MATCHING AND BYTE SWAPPING 64 x 36 x 2
(1)
COMMERCIAL TEMPERATURE RANGE
tSKEW2 CLKA tENS ENA tPAF tENH
1
2
tPAF (64-X) Long Words in FIFO1
AFA
CLKB
[64-(X+1)] Long Words in FIFO1
tENS ENB
tENH
3146 drw 19
NOTES: 1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW2, then AFA may transition HIGH one CLKB cycle later than shown. 2. FIFO1 Write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = LOW, MBB = LOW). 3. Port B size of long word is selected for FIFO1 read by SIZ1 = LOW, SIZ0 = LOW. If port B size is word or byte, tSKEW2 is referenced from the last word or byte read of the long word, respectively.
Figure 19. Timing for AFA when FIFO1 is Almost Full
tSKEW2 CLKB tENS ENB tPAF tENH
(1)
1
2
tPAF (64-X) Long Words in FIFO2
AFB
CLKA
[64-(X+1)] Long Words in FIFO2
tENS ENA
tENH
3146 drw 20
NOTES: 1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKB edge and rising CLKA edge is less than tSKEW2, then AFB may transition HIGH one CLKA cycle later than shown. 2. FIFO2 Write (CSB = LOW, W/RB = HIGH, MBB = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW). 3. Port B size of long word is selected for FIFO2 write by SIZ1 = LOW, SIZ0 = LOW. If port B size is word or byte, AFB is set LOW by the last word or byte read of the long word, respectively.
Figure 20. Timing for AFB when FIFO2 is Almost Full
32
IDT723614 CMOS SyncBiFIFOTM WITH BUS MATCHING AND BYTE SWAPPING 64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
CLKA
tENS
tENH
CSA
W/RA MBA ENA A0 - A35 tDS W1 tDH
CLKB
MBF1 CSB
W/RB SIZ1, SIZ0 ENB tEN B0 - B35 tMDV
tPMF
tPMF
tENS
tENH
tPMR FIFO1 Output Register
tDIS W1 (Remains valid in Mail1 Register after read)
3146 drw 21
NOTE: 1. Port B parity generation off (PGB = LOW).
Figure 21. Timing for Mail1 Register and MBF1 Flag
33
IDT723614 CMOS SyncBiFIFOTM WITH BUS MATCHING AND BYTE SWAPPING 64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
CLKB tENS
tENH
CSB
W/RB tSZS SIZ1, SIZ0 ENB tDS W1 tDH tSZH
B0 - B35
CLKA
MBF2 CSA
W/RA MBA
tPMF
tPMF
tENS ENA tEN A0 - A35 FIFO2 Output Register tMDV tPMR
tENH
tDIS W1 (Remains valid in Mail2 Register after read)
3146 drw 22
NOTE: 1. Port-A parity generation off (PGA = LOW).
Figure 22. Timing for Mail2 Register and MBF2 Flag
34
IDT723614 CMOS SyncBiFIFOTM WITH BUS MATCHING AND BYTE SWAPPING 64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
ODD/
EVEN
W/RA MBA PGA tPOPE tPOPE Valid Valid
tPEPE
tPEPE Valid
3146 drw 23
PEFA
Valid
Figure 23. ODD/EVEN W/RA, MBA, and PGA to PEFA Timing EVEN. R
ODD/
EVEN
W/RB SIZ1, SIZ0 PGB tPOPE tPOPE Valid Valid
tPEPE
tPEPE Valid
3146 drw 24
PEFB
Valid
Figure 24. ODD/EVEN W/RB, SIZ1, SIZ0, and PGB to PEFB Timing EVEN. R
35
IDT723614 CMOS SyncBiFIFOTM WITH BUS MATCHING AND BYTE SWAPPING 64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
ODD/
EVEN CSA
W/RA MBA PGA
LOW
tEN A8, A17, A26, A35
NOTE: 1. ENA is HIGH.
tPEPB tMDV Mail2 Data
tPOPB Generated Parity
tPEPB Generated Parity Mail2 Data
3146 drw 25
Figure 25. Parity Generation Timing when Reading from the Mail2 Register
ODD/
EVEN CSB
W/RB SIZ1, SIZ0 PGB
LOW
tEN B8, B17, B26, B35
NOTE: 1. ENB is HIGH.
tPEPB tMDV Mail1 Data
tPOPB Generated Parity
tPEPB Generated Parity
Mail1 Data
3146drw 26
Figure 26. Parity Generation Timing when Reading from the Mail1 Register
36
IDT723614 CMOS SyncBiFIFOTM WITH BUS MATCHING AND BYTE SWAPPING 64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
TYPICAL CHARACTERISTICS
SUPPLY CURRENT vs CLOCK FREQUENCY 400 VCC = 5.5 V VCC ==5.5 V VCC 5.5 V 350 f data = 1/2 f s T A = 25 C C L = 0 pF
300
VCC = 5 V
I CC(f) - Supply Current - mA
250
VCC = 4.5 V
200
150
100
50
0 0 10 20 30 40 50 60 70 80
f s - Clock Frequency - MHz
3146 drw 27
Figure 27
CALCULATING POWER DISSIPATION The ICC(f) current for the graph in Figure 27 was taken while simultaneously reading and writing the FIFO on the IDT723614 with CLKA and CLKB set to fs. All data inputs and data outputs change state during each clock cycle to consume the highest supply current. Data outputs were disconnected to normalize the graph to a zero-capacitance load. Once the capacitive lead per data-output channel is known, the power dissipation can be calculated with the equation below. With ICC(f) taken from Figure 28, the maximum power dissipation (PT) of the IDT723614 can be calculated by: PT = VCC x ICC(f) + (CL x VOH2 x fo) where: CL = fo = VOH = output capacitance load switching frequency of an output output high level voltage
When no reads or writes are occurring on the IDT723614, the power dissipated by a single clock (CLKA or CLKB) input running at frequency fs is calculated by: PT=VCC x fs x 0.290 mA/MHz
37
IDT723614 CMOS SyncBiFIFOTM WITH BUS MATCHING AND BYTE SWAPPING 64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
PARAMETER MEASUREMENT INFORMATION
5V
1.1 k From Output Under Test 680 30 pF
(1)
LOAD CIRCUIT
3V Timing Input tS Data, Enable Input 1.5 V 1.5 V GND th 3V 1.5 V GND Low-Level Input 1.5 V High-Level Input 1.5 V tW 1.5 V
3V GND 3V 1.5 V GND
VOLTAGE WAVEFORMS SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS PULSE DURATIONS
Output Enable tPLZ Low-Level Output
3V 1.5 V 1.5 V tPZL 1.5 V tPZH 1.5 V VOL VOH In-Phase Output GND 3 V Input 3V 1.5 V tPD 1.5 V 1.5 V GND tPD VOH 1.5 V VOL
High-Level Output
tPHZ
OV
VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES
3146 drw 28
NOTE: 1. Includes probe and jig capacitance.
Figure 28. Load Circuit and Voltage Waveforms
38
IDT723614 CMOS SyncBiFIFOTM WITH BUS MATCHING AND BYTE SWAPPING 64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT 723614 Device Type X Power XX Speed X Package X Process/ Temperature Range
BLANK
Commercial (0C to +70C)
PF PQF 15 20 30
Thin Quad Flat Pack (TQFP, PN120-1) Plastic Quad Flat Pack (PQFP, PQ132-1) Commercial Only Clock Cycle Time (tCLK) Speed in Nanoseconds
L
Low Power
723614 64 x 36 x 2 SyncBiFIFO
3146 drw 29
39

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